Speaker: Omer Khan, Associate Professor of Electrical and Computer Engineering from the University of Connecticut
Abstract: In the upcoming era where Moore's law is faltering, and artificial intelligence is taking over many facets of our lives, computer design faces new challenges to deliver performance and programmability. In addition, recent trends in the rise of malicious exploits, such as Spectre, Meltdown and Foreshadow attacks on commercial machines, processor security has emerged as a first order design criteria. In this talk I will outline my vision for a future multicore architecture that is capable of coping with the complex computational dynamics of temporally evolving graph and machine learning problems, while delivery tight security guarantees. I will advocate for building tiled multicores from grounds up with shared hardware resource isolation capabilities to create isolated clusters of cores for concurrent execution of co-located applications on a chip. For performance scaling, I will present a novel shared memory communication model that moves computation to data at the hardware level to accelerate inter-thread synchronization. Although the talk will focus on unordered algorithms for graphs and machine learning, I will also outline the idea of speculative execution within the proposed multicore framework to tackle hard to parallelize ordered algorithms. I will present evaluation of the performance and security tradeoffs using our prototype isolation framework developed on top of a real 72-core Tilera TILE-Gx72 machine, as well as a 1000-core scale simulated RISC-V multicore.
Bio: Omer Khan is an Associate Professor of Electrical and Computer Engineering at the University of Connecticut. Prior to joining UConn, he was a Postdoctoral Research Scientist at Massachusetts Institute of Technology. He received his Ph.D. in Electrical and Computer Engineering from the University of Massachusetts Amherst. He has nearly 20 years of computer architecture experience in academia and industry. At UConn, Omer leads the Computer Architecture Group, where he is developing cross-layer methods to improve the performance, security, and resiliency of processor architectures. He has published over 85 papers in competitive conferences, journals and workshops. He is the recipient of several competitive grants from US funding agencies, National Science Foundation, Department of Defense, and Semiconductor Research Corporation, as well as industry funding from NXP Semiconductors, Arm Research, Intel Corporation, and United Technologies Research Corporation. He is a member of the ACM and IEEE. Webpage: https://khan.engr.uconn.edu
This seminar is free and open to the public!
Wednesday, November 28, 2018 at 2:00pm
Chafee Hall, 244
10 Chaffee Rd, University of Rhode Island, Kingston, RI 02881, USA
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